create_project -force -part xc7k325tffg900-1 han325t_e902
add_files -fileset constrs_1 ../../../fpga/han325t/han325t_reve.xdc
add_files -fileset sources_1 ../../../fpga/han325t/kintex7_pll.v
add_files -fileset sources_1 ../../../fpga/han325t/led_7seg.v
add_files -fileset sources_1 ../../../fpga/han325t/led_toggle.v
add_files -fileset sources_1 ../../../fpga/han325t_e902/fpga_e902.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/cpu_cfig.h
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/clic_kid_golden_ports.v
add_files -fileset sources_1 ../../../ip/cpu/e902/biu/rtl/cr_ahbl_if.v
add_files -fileset sources_1 ../../../ip/cpu/e902/biu/rtl/cr_ahbl_req_arb.v
add_files -fileset sources_1 ../../../ip/cpu/e902/bmu/rtl/cr_bmu_dbus_if.v
add_files -fileset sources_1 ../../../ip/cpu/e902/bmu/rtl/cr_bmu_ibus_if.v
add_files -fileset sources_1 ../../../ip/cpu/e902/bmu/rtl/cr_bmu_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_arb.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_arb_kernel.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_busif.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_ctrl.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_ff1_onehot.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_kid.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_kid_dummy.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_sel.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clic/rtl/cr_clic_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clint/rtl/cr_clint_busif.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clint/rtl/cr_clint_regs.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clint/rtl/cr_clint_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clk/rtl/cr_clk_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clk/rtl/cr_clkrst_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/cr_core.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/cr_core_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_iui.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_lpmd.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_oreg.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_randclk.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_srst.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_status.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cp0/rtl/cr_cp0_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/openE902.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_bkpt.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_ctrl.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_ddc.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_inst_bkpt_lite.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_jtag2.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_pin.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_regs.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_sync.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_sync_level.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/had/rtl/cr_had_trace.v
add_files -fileset sources_1 ../../../ip/cpu/e902/biu/rtl/cr_iahbl_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_ibuf.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_ibuf_entry.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_ibusif.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_ifctrl.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_ifdp.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_randclk.v
add_files -fileset sources_1 ../../../ip/cpu/e902/ifu/rtl/cr_ifu_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_alu.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_branch.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_ctrl.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_decd.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_gated_clk_reg.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_gated_clk_reg_timing.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_hs_split.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_lockup.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_mad.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_oper.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_oper_gpr.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_pcgen.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_randclk.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_rbus.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_retire.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_special.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_vector.v
add_files -fileset sources_1 ../../../ip/cpu/e902/iu/rtl/cr_iu_wb.v
add_files -fileset sources_1 ../../../ip/cpu/e902/lsu/rtl/cr_lsu_ctrl.v
add_files -fileset sources_1 ../../../ip/cpu/e902/lsu/rtl/cr_lsu_dp.v
add_files -fileset sources_1 ../../../ip/cpu/e902/lsu/rtl/cr_lsu_randclk.v
add_files -fileset sources_1 ../../../ip/cpu/e902/lsu/rtl/cr_lsu_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/lsu/rtl/cr_lsu_unalign.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pmp/rtl/cr_pmp_acc_arb.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pmp/rtl/cr_pmp_comp_hit.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pmp/rtl/cr_pmp_enc.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pmp/rtl/cr_pmp_regs.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pmp/rtl/cr_pmp_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/pwrm/rtl/cr_pwrm_top_dummy.v
add_files -fileset sources_1 ../../../ip/cpu/e902/rst/rtl/cr_rst_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/biu/rtl/cr_sahbl_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/cpu/rtl/cr_sys_io.v
add_files -fileset sources_1 ../../../ip/cpu/e902/tcipif/rtl/cr_tcipif_behavior_bus.v
add_files -fileset sources_1 ../../../ip/cpu/e902/tcipif/rtl/cr_tcipif_dummy_bus.v
add_files -fileset sources_1 ../../../ip/cpu/e902/tcipif/rtl/cr_tcipif_top.v
add_files -fileset sources_1 ../../../ip/cpu/e902/clk/rtl/gated_clk_cell.v
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/common
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/ahb
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/apb
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/gpio
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/mem
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/pmu
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/smpu
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/timer
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/uart
add_files -fileset sources_1 ../../../ip/soc/thead_soc902/wic
set_property file_type "Verilog Header" [get_files ../../../ip/cpu/e902/cpu/rtl/cpu_cfig.h]
set_property is_global_include true     [get_files ../../../ip/cpu/e902/cpu/rtl/cpu_cfig.h]
set_property verilog_define [list FPGA] [get_filesets sources_1]
set_property include_dirs "../../../ip/cpu/e902/cpu/rtl" [current_fileset]
exit
